1. Field of the Invention
The present invention relates a system of generating scramble data and a method of generating scramble data, and particularly to a system of generating scramble data and a method of generating scramble data that can utilize a scramble engine to generate low correlation second scramble values according to first scramble values generated by a linear feedback shift register.
2. Description of the Prior Art
In the prior art, a system of generating scramble data utilizes a linear feedback shift register (LFSR) to generate a plurality of scramble values according to an initial value, e.g. 0x23 (0010_0011), 0x47 (0100_0111), 0x8F (1000_1111), and so on. Then, a logic gate executes a logic operation on the plurality of scramble values and data from a host to generate and output scramble data corresponding to the data from the host to a NAND flash.
The linear feedback shift register shifts left a scramble value one bit to generate a next scramble value. For example, the linear feedback shift register shifts left a scramble value 0x23 (0010_0011) one bit to generate a next scramble value 0x47 (0100_0111). But, it is noted that because the linear feedback shift register shifts left the scramble value 0x23 (0010_0011) one bit to generate the scramble value 0x47 (0100_0111), 7 identical bits exist between the scramble value 0x23 (0010_0011) and the scramble value 0x47 (0100_0111). That is to say, a correlation between the scramble value 0x23 (0010_0011) and the scramble value 0x47 (0100_0111) is high. Therefore, a correlation between any two adjacent scramble data generated by the logic gate according to scramble values generated by the linear feedback shift register is also high. Thus, scramble data generated by the logic gate can not satisfy a specification of the NAND flash.